forked from github/verilator
82 lines
1.6 KiB
Verilog
82 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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interface counter_io;
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logic [3:0] value;
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logic reset;
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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counter_io c1_data();
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counter_io c2_data();
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counter c1 (.clkm(clk),
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.c_data(c1_data),
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.i_value(4'h1));
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counter2 c2 (.clkm(clk),
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.c_data(c2_data),
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.i_value(4'h2));
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initial begin
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c1_data.value = 4'h4;
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c2_data.value = 4'h5;
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end
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc<2) begin
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c1_data.reset <= 1;
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c2_data.reset <= 1;
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end
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if (cyc==2) begin
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c1_data.reset <= 0;
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c2_data.reset <= 0;
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end
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if (cyc==20) begin
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$write("[%0t] c1 cyc%0d: %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset);
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$write("[%0t] c2 cyc%0d: %0x %0x\n", $time, cyc, c2_data.value, c2_data.reset);
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if (c1_data.value != 2) $stop;
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if (c2_data.value != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module counter
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(
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input clkm,
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counter_io c_data,
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input logic [3:0] i_value
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);
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always @ (posedge clkm) begin
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if (c_data.reset)
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c_data.value <= i_value;
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else
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c_data.value <= c_data.value + 1;
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end
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endmodule : counter
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module counter2(clkm, c_data, i_value);
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input clkm;
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counter_io c_data;
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input logic [3:0] i_value;
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always @ (posedge clkm) begin
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if (c_data.reset)
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c_data.value <= i_value;
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else
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c_data.value <= c_data.value + 1;
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end
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endmodule : counter2
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