forked from github/verilator
22 lines
438 B
Systemverilog
22 lines
438 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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generate
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begin
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eh2_ram dccm_bank (.*);
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end
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begin
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eh2_ram dccm_bank (.*); // Error: duplicate
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end
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endgenerate
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endmodule
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module eh2_ram ();
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endmodule
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