forked from github/verilator
112 lines
1.9 KiB
Systemverilog
112 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//verilator lint_off REALCVT
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`define testmod(modname) \
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module modname; \
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time t; \
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task check; t = 1ns; $write("%m %0t\n", t); endtask \
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endmodule
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`timescale 100s/1fs
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`testmod(sp2)
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`timescale 10s/1fs
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`testmod(sp1)
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`timescale 1s/1fs
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`testmod(sp0)
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`timescale 100ms/1fs
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`testmod(sm1)
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`timescale 10ms/1fs
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`testmod(sm2)
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`timescale 1ms/1fs
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`testmod(sm3)
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`timescale 100us/1fs
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`testmod(sm4)
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`timescale 10us/1fs
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`testmod(sm5)
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`timescale 1us/1fs
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`testmod(sm6)
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`timescale 100ns/1fs
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`testmod(sm7)
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`timescale 10ns/1fs
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`testmod(sm8)
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`timescale 1ns/1fs
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`testmod(sm9)
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`timescale 100ps/1fs
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`testmod(sm10)
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`timescale 10ps/1fs
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`testmod(sm11)
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`timescale 1ps/1fs
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`testmod(sm12)
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`timescale 100 fs/1fs
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`testmod(sm13)
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`timescale 10fs/1 fs
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`testmod(sm14)
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`timescale 1 fs / 1 fs // Comment
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`testmod(sm15)
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module r0;
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timeunit 10ns / 1ns;
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task check; $write("%m %0t\n", $time); endtask
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endmodule
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module r1;
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timeunit 10ns;
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timeprecision 1ns;
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task check; $write("%m %0t\n", $time); endtask
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endmodule
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module t;
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sp2 sp2();
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sp1 sp1();
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sp0 sp0();
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sm1 sm1();
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sm2 sm2();
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sm3 sm3();
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sm4 sm4();
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sm5 sm5();
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sm6 sm6();
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sm7 sm7();
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sm8 sm8();
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sm9 sm9();
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sm10 sm10();
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sm11 sm11();
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sm12 sm12();
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sm13 sm13();
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sm14 sm14();
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sm15 sm15();
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r0 r0();
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r1 r1();
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final begin
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sp2.check();
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sp1.check();
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sp0.check();
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sm1.check();
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sm2.check();
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sm3.check();
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sm4.check();
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sm5.check();
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sm6.check();
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sm7.check();
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sm8.check();
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sm9.check();
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sm10.check();
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sm11.check();
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sm12.check();
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sm13.check();
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sm14.check();
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sm15.check();
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r0.check();
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r1.check();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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