forked from github/verilator
960 lines
12 KiB
Plaintext
960 lines
12 KiB
Plaintext
`line 1 "t/t_preproc.v" 1
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`line 6 "t/t_preproc.v" 0
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`line 8 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc2.vh" 1
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`line 2 "t/t_preproc_inc2.vh" 0
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At file "t/t_preproc_inc2.vh" line 5
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`line 7 "t/t_preproc_inc2.vh" 0
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`line 1 "t/t_preproc_inc3.vh" 1
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`line 2 "inc3_a_filename_from_line_directive" 0
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`line 7 "inc3_a_filename_from_line_directive" 0
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At file "inc3_a_filename_from_line_directive" line 11
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`line 13 "inc3_a_filename_from_line_directive" 0
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`line 16 "inc3_a_filename_from_line_directive" 0
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`line 20 "inc3_a_filename_from_line_directive" 2
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`line 7 "t/t_preproc_inc2.vh" 0
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`line 9 "t/t_preproc_inc2.vh" 2
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`line 8 "t/t_preproc.v" 0
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`line 10 "t/t_preproc.v" 0
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`line 13 "t/t_preproc.v" 0
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/*verilator pass_thru comment*/
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`line 15 "t/t_preproc.v" 0
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/*verilator pass_thru_comment2*/
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`line 17 "t/t_preproc.v" 0
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`line 20 "t/t_preproc.v" 0
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wire [3:0] q = {
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1'b1 ,
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1'b0 ,
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1'b1 ,
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1'b1
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};
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`line 30 "t/t_preproc.v" 0
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text.
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`line 32 "t/t_preproc.v" 0
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foo bar
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foobar2
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`line 37 "t/t_preproc.v" 0
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`line 41 "t/t_preproc.v" 0
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`line 46 "t/t_preproc.v" 0
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first part
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`line 47 "t/t_preproc.v" 0
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second part
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`line 47 "t/t_preproc.v" 0
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third part
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{
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`line 48 "t/t_preproc.v" 0
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a,
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`line 48 "t/t_preproc.v" 0
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b,
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`line 48 "t/t_preproc.v" 0
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c}
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Line_Preproc_Check 49
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`line 51 "t/t_preproc.v" 0
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`line 53 "t/t_preproc.v" 0
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`line 55 "t/t_preproc.v" 0
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deep deep
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`line 59 "t/t_preproc.v" 0
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"Inside: `nosubst"
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"`nosubst"
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`line 64 "t/t_preproc.v" 0
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x y LLZZ x y
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p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s
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`line 70 "t/t_preproc.v" 0
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firstline comma","line LLZZ firstline comma","line
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`line 72 "t/t_preproc.v" 0
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x y LLZZ "x" y
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`line 75 "t/t_preproc.v" 0
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(a,b)(a,b)
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`line 78 "t/t_preproc.v" 0
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$display("left side: \"right side\"")
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`line 81 "t/t_preproc.v" 0
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bar_suffix more
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`line 84 "t/t_preproc.v" 0
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`line 86 "t/t_preproc.v" 0
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$c("Zap(\"",bug1,"\");");;
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`line 87 "t/t_preproc.v" 0
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$c("Zap(\"","bug2","\");");;
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`line 89 "t/t_preproc.v" 0
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`line 92 "t/t_preproc.v" 0
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`line 95 "t/t_preproc.v" 0
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initial begin
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$display("pre thrupre thrumid thrupost post: \"right side\"");
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$display("left side: \"right side\"");
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$display("left side: \"right side\"");
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$display("left_side: \"right_side\"");
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$display("na: \"right_side\"");
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$display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
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$display("na: \"nana\"");
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$display("left_side right_side: \"left_side right_side\"");
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$display(": \"\"");
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$display("left side: \"right side\"");
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$display("left side: \"right side\"");
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$display("standalone");
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`line 116 "t/t_preproc.v" 0
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$display("twoline: \"first second\"");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`line 126 "t/t_preproc.v" 0
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`line 129 "t/t_preproc.v" 0
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`line 134 "t/t_preproc.v" 0
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module add1 ( input wire d1, output wire o1);
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`line 135 "t/t_preproc.v" 0
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wire tmp_d1 = d1;
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`line 135 "t/t_preproc.v" 0
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wire tmp_o1 = tmp_d1 + 1;
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`line 135 "t/t_preproc.v" 0
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assign o1 = tmp_o1 ;
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endmodule
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module add2 ( input wire d2, output wire o2);
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`line 138 "t/t_preproc.v" 0
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wire tmp_d2 = d2;
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`line 138 "t/t_preproc.v" 0
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wire tmp_o2 = tmp_d2 + 1;
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`line 138 "t/t_preproc.v" 0
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assign o2 = tmp_o2 ;
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endmodule
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`line 141 "t/t_preproc.v" 0
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`line 147 "t/t_preproc.v" 0
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`line 152 "t/t_preproc.v" 0
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`line 152 "t/t_preproc.v" 0
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generate for (i=0; i<(3); i=i+1) begin
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`line 152 "t/t_preproc.v" 0
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psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";
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`line 152 "t/t_preproc.v" 0
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psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";
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`line 152 "t/t_preproc.v" 0
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end endgenerate
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`line 154 "t/t_preproc.v" 0
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module prot();
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`protected
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I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
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#nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
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`line 160 "t/t_preproc.v" 0
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`endprotected
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endmodule
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`line 164 "t/t_preproc.v" 0
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`line 174 "t/t_preproc.v" 0
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begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
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begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
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begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
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`line 178 "t/t_preproc.v" 0
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`line 181 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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`line 2 "t/t_preproc_inc4.vh" 0
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`line 6 "t/t_preproc_inc4.vh" 0
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`line 8 "t/t_preproc_inc4.vh" 2
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`line 181 "t/t_preproc.v" 0
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`line 182 "t/t_preproc.v" 0
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`line 185 "t/t_preproc.v" 0
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`line 187 "t/t_preproc.v" 0
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`line 191 "t/t_preproc.v" 0
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`line 194 "t/t_preproc.v" 0
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$blah("ab,cd","e,f");
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$blah(this.logfile,vec);
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$blah(this.logfile,vec[1,2,3]);
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$blah(this.logfile,{blah.name(), " is not foo"});
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`line 200 "t/t_preproc.v" 0
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`line 203 "t/t_preproc.v" 0
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`pragma foo = 1
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`default_nettype none
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`default_nettype uwire
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`line 207 "t/t_preproc.v" 0
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`line 210 "t/t_preproc.v" 0
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`line 214 "t/t_preproc.v" 0
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Line_Preproc_Check 214
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`line 216 "t/t_preproc.v" 0
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`line 219 "t/t_preproc.v" 0
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(p,q)
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`line 226 "t/t_preproc.v" 0
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(x,y)
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Line_Preproc_Check 227
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`line 229 "t/t_preproc.v" 0
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`line 232 "t/t_preproc.v" 0
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beginend
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beginend
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"beginend"
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`line 240 "t/t_preproc.v" 0
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`\esc`def
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`line 246 "t/t_preproc.v" 0
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Not a \`define
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`line 248 "t/t_preproc.v" 0
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x,y)--bee submacro has comma paren
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`line 256 "t/t_preproc.v" 0
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$display("10 %d %d", $bits(foo), 10);
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`line 261 "t/t_preproc.v" 0
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`line 266 "t/t_preproc.v" 0
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`line 269 "t/t_preproc.v" 0
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`line 283 "t/t_preproc.v" 0
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`line 283 "t/t_preproc.v" 0
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`line 283 "t/t_preproc.v" 0
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`line 283 "t/t_preproc.v" 0
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assign a3 = ~b3 ;
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`line 283 "t/t_preproc.v" 0
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`line 285 "t/t_preproc.v" 0
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\
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`line 294 "t/t_preproc.v" 0
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`line 294 "t/t_preproc.v" 0
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`line 294 "t/t_preproc.v" 0
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def i
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`line 296 "t/t_preproc.v" 0
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`line 298 "t/t_preproc.v" 0
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`line 302 "t/t_preproc.v" 0
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`line 308 "t/t_preproc.v" 0
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1 /*verilator NOT IN DEFINE*/ (nodef)
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2 /*verilator PART OF DEFINE*/ (hasdef)
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3
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`line 310 "t/t_preproc.v" 0
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/*verilator NOT PART
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OF DEFINE*/ (nodef)
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`line 311 "t/t_preproc.v" 0
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4
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`line 311 "t/t_preproc.v" 0
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/*verilator PART
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OF DEFINE*/ (nodef)
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`line 312 "t/t_preproc.v" 0
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5 also in
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`line 312 "t/t_preproc.v" 0
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also3 (nodef)
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HAS a NEW
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`line 315 "t/t_preproc.v" 0
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LINE
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`line 317 "t/t_preproc.v" 0
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`line 319 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 335 "t/t_preproc.v" 0
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EXP: clxx_scen
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clxx_scen
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EXP: clxx_scen
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"clxx_scen"
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EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
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`line 341 "t/t_preproc.v" 0
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do
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`line 341 "t/t_preproc.v" 0
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`line 341 "t/t_preproc.v" 0
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`line 341 "t/t_preproc.v" 0
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`line 341 "t/t_preproc.v" 0
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`line 341 "t/t_preproc.v" 0
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if (start("t/t_preproc.v", 341)) begin
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`line 341 "t/t_preproc.v" 0
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`line 341 "t/t_preproc.v" 0
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message({"Blah-", "clx_scen", " end"});
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end
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`line 341 "t/t_preproc.v" 0
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`line 341 "t/t_preproc.v" 0
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while(0);
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`line 349 "t/t_preproc.v" 0
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`line 350 "t/t_preproc.v" 0
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EXP: This is fooed
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This is fooed
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EXP: This is fooed_2
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This is fooed_2
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`line 357 "t/t_preproc.v" 0
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np
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np
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`line 368 "t/t_preproc.v" 0
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`line 379 "t/t_preproc.v" 0
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`line 383 "t/t_preproc.v" 0
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hello3hello3hello3
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hello4hello4hello4hello4
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`line 389 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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`line 2 "t/t_preproc_inc4.vh" 0
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`line 6 "t/t_preproc_inc4.vh" 0
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`line 8 "t/t_preproc_inc4.vh" 2
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`line 389 "t/t_preproc.v" 0
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`line 390 "t/t_preproc.v" 0
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`line 398 "t/t_preproc.v" 0
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Line_Preproc_Check 402
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Line_Preproc_Check 408
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"FOO \
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BAR " "arg_line1 \
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arg_line2" "FOO \
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BAR "
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`line 411 "t/t_preproc.v" 0
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Line_Preproc_Check 411
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`line 415 "t/t_preproc.v" 0
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abc
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`line 425 "t/t_preproc.v" 0
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EXP: sonet_frame
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sonet_frame
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`line 431 "t/t_preproc.v" 0
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EXP: sonet_frame
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sonet_frame
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EXP: sonet_frame
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sonet_frame
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`line 441 "t/t_preproc.v" 0
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EXP: module zzz ; endmodule
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module zzz ; endmodule
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module zzz ; endmodule
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`line 448 "t/t_preproc.v" 0
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EXP: module a_b ; endmodule
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module a_b ; endmodule
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module a_b ; endmodule
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`line 453 "t/t_preproc.v" 0
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integer foo;
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module t;
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initial begin : \`LEX_CAT(a[0],_assignment)
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`line 465 "t/t_preproc.v" 0
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end
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initial begin : \a[0]_assignment_a[1]
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`line 472 "t/t_preproc.v" 0
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end
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initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end
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initial begin : \`CAT(ff,bb)
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`line 486 "t/t_preproc.v" 0
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end
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initial begin : \`zzz
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`line 492 "t/t_preproc.v" 0
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end
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initial begin : \`FOO
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`line 499 "t/t_preproc.v" 0
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$write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end
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initial begin : \xx`FOO
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`line 501 "t/t_preproc.v" 0
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$write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end
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initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end
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initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end
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initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
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initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
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initial $write("Slashed=`%s'\n", "1//2.3");
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initial
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`line 532 "t/t_preproc.v" 0
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$display("%s%s","a1","b2c3\n");
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endmodule
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`line 535 "t/t_preproc.v" 0
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`line 538 "t/t_preproc.v" 0
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$display("RAM0");
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$display("CPU");
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`line 543 "t/t_preproc.v" 0
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`line 548 "t/t_preproc.v" 0
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XXE_FAMILY = XXE_
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$display("XXE_ is defined");
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`line 555 "t/t_preproc.v" 0
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XYE_FAMILY = XYE_
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$display("XYE_ is defined");
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`line 562 "t/t_preproc.v" 0
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XXS_FAMILY = XXS_some
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$display("XXS_some is defined");
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`line 569 "t/t_preproc.v" 0
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XYS_FAMILY = XYS_foo
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$display("XYS_foo is defined");
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`line 576 "t/t_preproc.v" 0
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`line 578 "t/t_preproc.v" 0
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`line 586 "t/t_preproc.v" 0
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`line 593 "t/t_preproc.v" 0
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`line 600 "t/t_preproc.v" 0
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`line 607 "t/t_preproc.v" 0
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`line 609 "t/t_preproc.v" 0
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`line 611 "t/t_preproc.v" 0
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(.mySig (myInterface.pa5),
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`line 615 "t/t_preproc.v" 0
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`line 618 "t/t_preproc.v" 0
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`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
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`line 621 "t/t_preproc.v" 0
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`line 629 "t/t_preproc.v" 0
|
|
module pcc2_cfg;
|
|
generate
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`line 631 "t/t_preproc.v" 0
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|
covergroup a @(posedge b);
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`line 631 "t/t_preproc.v" 0
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c: coverpoint d iff ((c) === 1'b1); endgroup
|
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`line 631 "t/t_preproc.v" 0
|
|
a u_a;
|
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`line 631 "t/t_preproc.v" 0
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|
initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
|
|
endgenerate
|
|
endmodule
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`line 635 "t/t_preproc.v" 0
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predef 0 0
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predef 1 1
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predef 2 2
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predef 3 3
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predef 10 10
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predef 11 11
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predef 20 20
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predef 21 21
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predef 22 22
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predef 23 23
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predef -2 -2
|
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predef -1 -1
|
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predef 0 0
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predef 1 1
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predef 2 2
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`line 657 "t/t_preproc.v" 2
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