forked from github/verilator
16 lines
416 B
Systemverilog
16 lines
416 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (d, clk);
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input d;
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input clk;
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always @ (posedge clk) begin
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if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >- 0
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if ($past(d, 10000)) $stop; // TICKCOUNT
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end
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endmodule
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