forked from github/verilator
d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
20 lines
409 B
Systemverilog
20 lines
409 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2018 by Alex Solomatnikov
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
sub #(.REAL(2.0)) sub;
|
|
endmodule
|
|
|
|
module sub ();
|
|
parameter REAL = 0.0;
|
|
|
|
initial begin
|
|
$display("REAL %g", REAL);
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|