forked from github/verilator
26 lines
589 B
Systemverilog
26 lines
589 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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sub sub ();
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endmodule
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module sub;
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//verilator no_inline_module
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string scope;
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initial begin
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scope = $sformatf("%m");
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$write("[%0t] In %s\n", $time, scope);
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`ifdef VERILATOR
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if (scope != "top.l2Name.sub") $stop;
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`else
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if (scope != "top.t.sub") $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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