forked from github/verilator
18 lines
485 B
Systemverilog
18 lines
485 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg a;
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initial begin
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$unknown_sys_task_call_to_be_bbox("blah");
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$unkown_sys_task_call_noarg;
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a = $unknown_sys_func_call(23);
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a = $unknown_sys_func_call_noarg;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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