forked from github/verilator
27 lines
954 B
Perl
Executable File
27 lines
954 B
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => [qw(--lint-only)],
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verilator_make_gcc => 0,
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make_top_shell => 0,
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make_main => 0,
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fails => $Self->{vlt_all},
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expect =>
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'%Warning-LITENDIAN: t/t_metacmt_onoff.v:\d+: Little bit endian vector: MSB < LSB of bit range: 0:1
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%Warning-LITENDIAN: Use "/\* verilator lint_off LITENDIAN \*/" and lint_on around source to disable this message.
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%Warning-LITENDIAN: t/t_metacmt_onoff.v:\d+: Little bit endian vector: MSB < LSB of bit range: 0:3
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%Error: Exiting due to.*',
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);
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ok(1);
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1;
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