forked from github/verilator
29 lines
1.1 KiB
Perl
Executable File
29 lines
1.1 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(vlt_all => 1);
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compile(
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v_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"],
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fails => 1,
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verilator_make_gcc => 0,
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make_top_shell => 0,
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make_main => 0,
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expect =>
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'%Warning-BLKSEQ: t/t_lint_blksync_bad.v:\d+: Blocking assignments \(=\) in sequential \(flop or latch\) block; suggest delayed assignments \(<=\).
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%Warning-BLKSEQ: Use .* to disable this message.
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%Warning-COMBDLY: t/t_lint_blksync_bad.v:\d+: Delayed assignments \(<=\) in non-clocked \(non flop or latch\) block; suggest blocking assignments \(=\).
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%Warning-COMBDLY: \*\*\* See the manual before disabling this,
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%Warning-COMBDLY: else you may end up with different sim results.
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%Error: Exiting due to.*',
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);
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ok(1);
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1;
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