forked from github/verilator
58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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typedef int unit_type_t;
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function [3:0] unit_plusone(input [3:0] i);
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unit_plusone = i+1;
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endfunction
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package p;
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typedef int package_type_t;
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function [3:0] plusone(input [3:0] i);
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plusone = i+1;
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endfunction
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endpackage
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package p2;
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typedef int package2_type_t;
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function [3:0] plustwo(input [3:0] i);
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plustwo = i+2;
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endfunction
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endpackage
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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unit_type_t vu;
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$unit::unit_type_t vdu;
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p::package_type_t vp;
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t2 t2 ();
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initial begin
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if (unit_plusone(1) !== 2) $stop;
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if ($unit::unit_plusone(1) !== 2) $stop;
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if (p::plusone(1) !== 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module t2;
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import p::*;
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import p2::plustwo;
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import p2::package2_type_t;
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package_type_t vp;
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package2_type_t vp2;
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initial begin
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if (plusone(1) !== 2) $stop;
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if (plustwo(1) !== 3) $stop;
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end
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endmodule
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