forked from github/verilator
22 lines
1.1 KiB
Plaintext
22 lines
1.1 KiB
Plaintext
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
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: ... In instance t
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w = '0;
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^
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
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: ... In instance t
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o = '0;
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^
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
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: ... In instance t
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oa = '0;
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^~
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
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: ... In instance t
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wo = '0;
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^~
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%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
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: ... In instance t
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woa = '0;
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^~~
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%Error: Exiting due to
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