forked from github/verilator
37 lines
761 B
Systemverilog
37 lines
761 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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o, oa, ro, roa, wo, woa
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);
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wire w;
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reg r;
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output o;
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output [1:0] oa;
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output reg ro;
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output reg [1:0] roa;
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output wire wo;
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output wire [1:0] woa;
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//1800 only:
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//output var vo;
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//output var [1:0] voa;
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initial begin
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w = '0; // Error
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o = '0; // Error
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oa = '0; // Error
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wo = '0; // Error
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woa = '0; // Error
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r = '0; // Not an error
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ro = '0; // Not an error
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roa = '0; // Not an error
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//vo = '0; // Not an error
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//voa = '0; // Not an error
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end
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endmodule
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