forked from github/verilator
22 lines
1.1 KiB
Plaintext
22 lines
1.1 KiB
Plaintext
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
|
|
: ... In instance t
|
|
w = '0;
|
|
^
|
|
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
|
|
: ... In instance t
|
|
o = '0;
|
|
^
|
|
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
|
|
: ... In instance t
|
|
oa = '0;
|
|
^~
|
|
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
|
|
: ... In instance t
|
|
wo = '0;
|
|
^~
|
|
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
|
|
: ... In instance t
|
|
woa = '0;
|
|
^~~
|
|
%Error: Exiting due to
|