forked from github/verilator
75 lines
940 B
Systemverilog
75 lines
940 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t
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(
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/*AUTOARG*/
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// Outputs
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o, oi, og, org,
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// Inputs
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i, oi
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);
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reg a;
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reg a;
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integer l;
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integer l;
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bit b;
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bit b;
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output o;
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output o;
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input i;
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input i;
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output oi;
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input oi;
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output og;
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reg og;
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reg og;
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output reg org;
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output reg org;
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sub0 sub0(.*);
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sub1 sub1(.*);
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sub2 sub2(.*);
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sub3 sub3(.*);
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endmodule
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module sub0
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(
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bad_duport,
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bad_duport
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);
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output bad_duport;
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endmodule
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module sub1
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(
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bad_mixport,
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output bad_mixport
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);
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endmodule
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module sub2
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(
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output bad_reout_port
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);
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output bad_reout_port;
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endmodule
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module sub3
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(output wire bad_rewire,
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output reg bad_rereg
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);
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wire bad_rewire;
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reg bad_rereg;
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endmodule
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