verilator/test_regress/t/t_var_bad_sv.v
2009-09-07 15:54:12 -04:00

10 lines
214 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
reg do;
mod mod (.do(bar));
endmodule