forked from github/verilator
51 lines
1.4 KiB
Perl
Executable File
51 lines
1.4 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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use IO::File;
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#use Data::Dumper;
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use strict;
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use vars qw($Self);
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scenarios(simulator => 1);
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sub gen {
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my $filename = shift;
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my $fh = IO::File->new(">$filename");
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$fh->print(chr(0xEF).chr(0xBB).chr(0xBF)); # BOM
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$fh->print("// Bom\n");
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$fh->print("// Generated by t_unicode.pl\n");
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$fh->print("module t;\n");
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$fh->print(" // Chinese "
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.chr(0xe8).chr(0xaf).chr(0x84).chr(0xe8).chr(0xae).chr(0xba) # Comment
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."\n");
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$fh->print(" initial begin\n");
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$fh->print(" \$write(\"Hello "
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.chr(0xe4).chr(0xb8).chr(0x96).chr(0xe7).chr(0x95).chr(0x8c) # World
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."\\n\");\n");
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$fh->print(" \$write(\"*-* All Finished *-*\\n\");\n");
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$fh->print(" \$finish;\n");
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$fh->print(" end\n");
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$fh->print("endmodule\n");
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}
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top_filename("$Self->{obj_dir}/t_unicode.v");
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gen($Self->{top_filename});
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compile(
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);
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execute(
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check_finished => 1,
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expect => q{Hello \344\270\226\347\225\214.*},
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);
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ok(1);
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1;
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