forked from github/verilator
32 lines
543 B
Systemverilog
32 lines
543 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inouts
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AVDD, AVSS
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);
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inout AVDD;
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inout AVSS;
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sub sub (/*AUTOINST*/
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// Inouts
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.AVDD (AVDD),
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.AVSS (AVSS));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (/*AUTOARG*/
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// Inouts
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AVDD, AVSS
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);
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// verilator no_inline_module
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inout AVDD;
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inout AVSS;
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endmodule
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