forked from github/verilator
21 lines
358 B
Systemverilog
21 lines
358 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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module t(/*AUTOARG*/
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// Outputs
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o,
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// Inputs
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i
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);
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input i;
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output o;
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sub sub(i, o);
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endmodule
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module sub(input i, output o);
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assign o = (i===1'bz) ? 1'b0 : i;
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endmodule
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