forked from github/verilator
45 lines
1.1 KiB
C++
45 lines
1.1 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include VM_PREFIX_INCLUDE
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unsigned long long main_time = 0;
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double sc_time_stamp() { return ((double)main_time) / VL_TIME_MULTIPLIER; }
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int main(int argc, char** argv, char** env) {
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VM_PREFIX* top = new VM_PREFIX("top");
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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VerilatedVcdC* tfp = new VerilatedVcdC;
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tfp->set_time_resolution("1ps");
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tfp->set_time_unit("1ns");
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top->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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top->clk = 0;
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while (main_time < 190 * VL_TIME_MULTIPLIER) {
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top->clk = !top->clk;
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top->eval();
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tfp->dump((unsigned int)(main_time));
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// Advance by 0.5 time units, to make sure our fractional
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// time is working correctly
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main_time += VL_TIME_MULTIPLIER / 2;
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}
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tfp->close();
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top->final();
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printf("*-* All Finished *-*\n");
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return 0;
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}
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