forked from github/verilator
39 lines
1.3 KiB
Perl
Executable File
39 lines
1.3 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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top_filename("t/t_sys_readmem.v");
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# Use random reset to ensure we're fully initializing arrays before
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# $writememh, to avoid miscompares with X's on 4-state simulators.
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$Self->{verilated_randReset} = 2; # 2 == truly random
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compile(v_flags2 => [
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"+define+WRITEMEM_READ_BACK=1",
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"+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"",
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"+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"",
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"+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"",
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"+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"",
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"+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"",
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]);
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execute(
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check_finished => 1,
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);
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for (my $i = 1; $i <= 5; $i++) {
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my $gold = "$Self->{t_dir}/t_sys_writemem.gold${i}.mem";
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my $out = "$Self->{obj_dir}/tmp${i}.mem";
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files_identical($out, $gold);
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}
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ok(1);
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1;
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