forked from github/verilator
35 lines
609 B
Systemverilog
35 lines
609 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] time64;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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end
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else if (cyc<10) begin
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end
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else if (cyc<90) begin
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time64 = $time;
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if ($stime != time64[31:0]) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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