forked from github/verilator
34 lines
675 B
Systemverilog
34 lines
675 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t;
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integer i;
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initial begin
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`ifndef VERILATOR
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`ifndef VCS
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`ifndef NC
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$system(); // Legal per spec, but not supported everywhere and nonsensical
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`endif
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`endif
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`endif
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$system("exit 0");
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$system("echo hello");
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`ifndef VCS
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i = $system("exit 0");
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if (i!==0) $stop;
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i = $system("exit 10");
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if (i!==10) $stop;
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i = $system("exit 20"); // Wide
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if (i!==20) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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