forked from github/verilator
18 lines
365 B
Systemverilog
18 lines
365 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg [175:0] hex [15:0];
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integer i;
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initial begin
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$readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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