forked from github/verilator
18 lines
437 B
Systemverilog
18 lines
437 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t;
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parameter [ BMSB : BLSB ] B = A[23:20]; // 3
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parameter A = 32'h12345678;
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parameter BLSB = A[16+:4]; // 4
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parameter BMSB = A[7:4]; // 7
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initial begin
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if (B !== 4'h3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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