forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
19 lines
388 B
Systemverilog
19 lines
388 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003-2007 by Wilson Snyder.
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module t (clk);
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input clk;
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reg [43:0] mi;
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reg [3:0] sel2;
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reg [0:22] backwd;
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always @ (posedge clk) begin
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mi = 44'h123;
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sel2 = mi[1:4];
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$write ("Bad select %x\n", sel2);
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end
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endmodule
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