forked from github/verilator
69 lines
1.9 KiB
Systemverilog
69 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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module secret (
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input [31:0] accum_in,
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output wire [31:0] accum_out,
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input accum_bypass,
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output [31:0] accum_bypass_out,
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input s1_in,
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output logic s1_out,
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input [1:0] s2_in,
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output logic [1:0] s2_out,
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input [7:0] s8_in,
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output logic [7:0] s8_out,
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input [32:0] s33_in,
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output logic [32:0] s33_out,
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input [63:0] s64_in,
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output logic [63:0] s64_out,
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input [64:0] s65_in,
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output logic [64:0] s65_out,
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input [128:0] s129_in,
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output logic [128:0] s129_out,
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input [3:0] [31:0] s4x32_in,
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output logic [3:0] [31:0] s4x32_out,
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input clk);
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logic [31:0] secret_accum_q = 0;
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logic [31:0] secret_value = 7;
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initial $display("created %m");
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always @(posedge clk) begin
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secret_accum_q <= secret_accum_q + accum_in + secret_value;
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end
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// Test combinatorial paths of different sizes
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always @(*) begin
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s1_out = s1_in;
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s2_out = s2_in;
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s8_out = s8_in;
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s64_out = s64_in;
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s65_out = s65_in;
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s129_out = s129_in;
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s4x32_out = s4x32_in;
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end
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sub sub (.sub_in(s33_in), .sub_out(s33_out));
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// Test sequential path
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assign accum_out = secret_accum_q;
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// Test mixed combinatorial/sequential path
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assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
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final $display("destroying %m");
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endmodule
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module sub (
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input [32:0] sub_in,
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output [32:0] sub_out);
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/*verilator no_inline_module*/
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assign sub_out = sub_in;
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endmodule
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