forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
17 lines
322 B
Systemverilog
17 lines
322 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t;
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`define DUP fred
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`define DUP barney
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`define DUPP paramed(x) (x)
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`define DUPP paramed(x,z) (x*z)
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initial $stop; // Should have failed
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endmodule
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