forked from github/verilator
21 lines
466 B
Systemverilog
21 lines
466 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (/*AUTOARG*/);
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// verilator lint_off WIDTH
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reg [6:0] myreg1;
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initial begin
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myreg1 = # 100 7'd0;
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myreg1 = # 100 'b0; // [#] [100] ['b0]
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myreg1 = #100'b0; // [#] [100] ['b0]
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myreg1 = 100'b0;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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