forked from github/verilator
26 lines
416 B
Systemverilog
26 lines
416 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Driss Hafdi.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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test #(.param(32'd0)) test_i;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module test
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#(
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parameter logic param = 1'b0
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) ();
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endmodule
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