forked from github/verilator
29 lines
646 B
Systemverilog
29 lines
646 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Driss Hafdi.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [7:0] digit = getDigit(4'd1);
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initial begin
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if (digit != "1") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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function automatic logic[7:0] getDigit(logic[3:0] d);
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localparam logic[7:0] digits[10]
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= '{
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"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"
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};
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return digits[d];
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endfunction
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