forked from github/verilator
28 lines
641 B
Systemverilog
28 lines
641 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Wilson Snyder.
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module t;
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function integer bottom_4bits;
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input [7:0] i;
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bottom_4bits = 0;
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bottom_4bits[3:0] = i[3:0];
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endfunction
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function integer bottom_2_unknown;
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input [7:0] i;
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// bottom_4bits = 0; 'x
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bottom_2_unknown[1:0] = i[1:0];
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endfunction
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localparam p = bottom_4bits(8'h13);
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localparam bu = bottom_2_unknown(8'h13);
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initial begin
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if (p != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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