forked from github/verilator
72 lines
1.3 KiB
Systemverilog
72 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett
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// see bug 591
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package pkg1;
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parameter PARAM2 = 16;
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parameter PARAM3 = 16;
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endpackage : pkg1
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package pkg10;
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import pkg1::*;
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import pkg1::*; // Ignore if already
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`ifdef T_PACKAGE_EXPORT
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export *::*; // Not supported on all simulators
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`endif
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parameter PARAM1 = 8;
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endpackage
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package pkg11;
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import pkg10::*;
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endpackage
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package pkg20;
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import pkg1::*;
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`ifdef T_PACKAGE_EXPORT
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export pkg1::*;
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`endif
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parameter PARAM1 = 8;
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endpackage
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package pkg21;
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import pkg20::*;
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endpackage
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package pkg30;
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import pkg1::*;
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`ifdef T_PACKAGE_EXPORT
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export pkg1::PARAM2;
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export pkg1::PARAM3;
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`endif
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parameter PARAM1 = 8;
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endpackage
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package pkg31;
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import pkg30::*;
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endpackage
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [pkg11::PARAM1 : 0] bus11;
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reg [pkg11::PARAM2 : 0] bus12;
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reg [pkg11::PARAM3 : 0] bus13;
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reg [pkg21::PARAM1 : 0] bus21;
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reg [pkg21::PARAM2 : 0] bus22;
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reg [pkg21::PARAM3 : 0] bus23;
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reg [pkg31::PARAM1 : 0] bus31;
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reg [pkg31::PARAM2 : 0] bus32;
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reg [pkg31::PARAM3 : 0] bus33;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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