forked from github/verilator
45 lines
977 B
Systemverilog
45 lines
977 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork.
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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interface a_if ();
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string s;
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endinterface
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module sub (output string s);
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initial s = $sformatf("%m");
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endmodule
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module t
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(
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clk
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);
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input clk;
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string str [2:0][1:0];
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a_if iface [2:0][1:0];
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sub i_sub[2:0][1:0] (.s(str));
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initial begin
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// TODO make self checking
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$display(iface[0][0]);
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$display(iface[0][1]);
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$display(iface[1][0]);
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$display(iface[1][1]);
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$display(iface[2][0]);
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$display(iface[2][1]);
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$display(str[0][0]);
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$display(str[0][1]);
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$display(str[1][0]);
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$display(str[1][1]);
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$display(str[2][0]);
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$display(str[2][1]);
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end
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endmodule
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