forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
57 lines
1.2 KiB
Systemverilog
57 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg signed [64+15:0] data;
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integer i;
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integer b;
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reg signed [64+15:0] srs;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==2) begin
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data <= 80'h0;
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data[75] <= 1'b1;
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data[10] <= 1'b1;
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end
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if (cyc==3) begin
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for (i=0; i<85; i=i+1) begin
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srs = data>>>i;
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//$write (" %x >>> %d == %x\n",data,i,srs);
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for (b=0; b<80; b=b+1) begin
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if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
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end
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end
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end
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if (cyc==10) begin
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data <= 80'h0;
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data[79] <= 1'b1;
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data[10] <= 1'b1;
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end
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if (cyc==12) begin
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for (i=0; i<85; i=i+1) begin
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srs = data>>>i;
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//$write (" %x >>> %d == %x\n",data,i,srs);
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for (b=0; b<80; b=b+1) begin
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if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
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end
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end
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end
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if (cyc==20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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