forked from github/verilator
38 lines
592 B
Systemverilog
38 lines
592 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t
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(
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output wire o,
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input wire i,
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input wire i2
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);
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sub
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#(, // Not found
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.NEXIST(1), // Not found
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.P(2),
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.P(3)) // Dup
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sub (.o(o),
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.i(i),
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.i(i2), // Dup
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.nexist(i2) // Not found
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);
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endmodule
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module sub
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#(parameter P=1,
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parameter EXIST=9)
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(
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output wire o,
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input wire i,
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input wire exists
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);
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assign o = ~i;
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endmodule
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