forked from github/verilator
19 lines
343 B
Systemverilog
19 lines
343 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (a,z);
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input a;
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output z;
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assign b = 1'b1;
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or OR0 (nt0, a, b);
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logic [1:0] dummy_ip;
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assign {dummy1, dummy2} = dummy_ip;
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assign z = nt0;
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endmodule
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