forked from github/verilator
41 lines
1.1 KiB
Systemverilog
41 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t;
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integer value = 19;
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initial begin
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if (value==1) begin end
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else if (value==2) begin end
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else if (value==3) begin end
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else if (value==4) begin end
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else if (value==5) begin end
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else if (value==6) begin end
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else if (value==7) begin end
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else if (value==8) begin end
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else if (value==9) begin end
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else if (value==10) begin end
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else if (value==11) begin end // Warn about this one
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else if (value==12) begin end
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end
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initial begin
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unique0 if (value==1) begin end
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else if (value==2) begin end
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else if (value==3) begin end
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else if (value==4) begin end
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else if (value==5) begin end
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else if (value==6) begin end
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else if (value==7) begin end
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else if (value==8) begin end
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else if (value==9) begin end
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else if (value==10) begin end
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else if (value==11) begin end // Warn about this one
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else if (value==12) begin end
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end
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endmodule
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