forked from github/verilator
26 lines
465 B
Systemverilog
26 lines
465 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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interface ifc;
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integer ok;
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modport out_modport (output ok);
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endinterface
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module t (/*AUTOARG*/);
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ifc itop();
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counter_ansi c1 (.isub(itop),
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.i_value(4'h4));
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endmodule
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module counter_ansi
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(
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ifc.oop_modport isub, // Bad
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input logic [3:0] i_value
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);
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endmodule
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