forked from github/verilator
86 lines
1.8 KiB
Systemverilog
86 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#1631
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Julien Margetts.
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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localparam N = 4;
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wire [7:0] cval1[0:N-1];
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wire [7:0] cval2[N-1:0];
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wire [7:0] cval3[0:N-1];
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wire [7:0] cval4[N-1:0];
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wire [3:0] inc;
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assign inc = 4'b0001;
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// verilator lint_off LITENDIAN
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COUNTER UCOUNTER1[N-1:0]
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(
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.clk (clk),
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.inc (inc),
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.o (cval1) // Twisted
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);
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COUNTER UCOUNTER2[N-1:0]
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(
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.clk (clk),
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.inc (inc),
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.o (cval2) // Matches
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);
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COUNTER UCOUNTER3[0:N-1]
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(
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.clk (clk),
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.inc (inc),
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.o (cval3) // Matches
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);
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COUNTER UCOUNTER4[0:N-1]
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(
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.clk (clk),
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.inc (inc),
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.o (cval4) // Twisted
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);
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always @(posedge clk) begin
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if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0]))
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$stop;
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if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] +
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cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0)
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$stop;
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`ifdef TEST_VERBOSE
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$display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]);
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$display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]);
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$display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]);
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$display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]);
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`endif
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if (cval1[0] + cval1[3] > 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module COUNTER
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(
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input clk,
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input inc,
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output reg [7:0] o
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);
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initial o = 8'd0; // No reset input
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always @(posedge clk) if (inc) o <= o + 1;
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endmodule
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