forked from github/verilator
102 lines
2.2 KiB
Systemverilog
102 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: initial edge issue
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//
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// The module initial_edge drives the output "res" high when the reset signal,
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// rst, goes high.
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//
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// The module initial_edge_n drives the output "res_n" high when the reset
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// signal, rst_n, goes low.
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//
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// For 4-state simulators, that edge occurs when the initial value of rst_n,
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// X, goes to zero. However, by default for Verilator, being 2-state, the
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// initial value is zero, so no edge is seen.
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//
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// This is not a bug in verilator (it is bad design to rely on an edge
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// transition from an unitialized signal), but the problem is that there are
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// quite a few instances of code out there that seems to be dependent on this
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// behaviour to get out of reset.
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//
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// The Verilator --x-initial-edge flag causes these initial edges to trigger,
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// thus matching the behaviour of a 4-state simulator. This is reportedly also
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// the behaviour of commercial cycle accurate modelling tools as well.
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2012 by Wilson Snyder.
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`timescale 1ns/1ns
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire res;
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wire res_n;
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reg rst;
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reg rst_n;
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integer count = 0;
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initial_edge i_edge (.res (res),
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.rst (rst));
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initial_edge_n i_edge_n (.res_n (res_n),
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.rst_n (rst_n));
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// run for 3 cycles, with one cycle of reset.
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always @(posedge clk) begin
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rst <= (count == 0) ? 1 : 0;
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rst_n <= (count == 0) ? 0 : 1;
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if (count == 3) begin
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if ((res == 1) && (res_n == 1)) begin
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$write ("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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`ifdef TEST_VERBOSE
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$write ("FAILED: res = %b, res_n = %b\n", res, res_n);
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`endif
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$stop;
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end
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end
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count = count + 1;
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end
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endmodule
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module initial_edge_n (res_n,
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rst_n);
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output res_n;
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input rst_n;
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reg res_n = 1'b0;
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always @(negedge rst_n) begin
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if (rst_n == 1'b0) begin
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res_n <= 1'b1;
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end
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end
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endmodule // initial_edge_n
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module initial_edge (res,
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rst);
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output res;
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input rst;
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reg res = 1'b0;
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always @(posedge rst) begin
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if (rst == 1'b1) begin
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res <= 1'b1;
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end
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end
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endmodule // initial_edge
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