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87 lines
1.8 KiB
Systemverilog
87 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [31:0] wr_data;
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reg wr_en;
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wire [31:0] rd_data;
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wire [1:0] rd_guards;
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wire [1:0] rd_guardsok;
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regfile regfile (/*AUTOINST*/
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// Outputs
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.rd_data (rd_data[31:0]),
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.rd_guards (rd_guards[1:0]),
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.rd_guardsok (rd_guardsok[1:0]),
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// Inputs
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.wr_data (wr_data[31:0]),
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.wr_en (wr_en),
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.clk (clk));
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initial wr_en = 0;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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if (!rd_guards[0]) $stop;
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if (!rd_guardsok[0]) $stop;
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wr_en <= 1'b1;
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wr_data <= 32'hfeedf;
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end
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if (cyc==2) begin
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wr_en <= 0;
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end
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if (cyc==3) begin
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wr_en <= 0;
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if (rd_data != 32'hfeedf) $stop;
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if (rd_guards != 2'b11) $stop;
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if (rd_guardsok != 2'b11) $stop;
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end
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if (cyc==4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module regfile (
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input [31:0] wr_data,
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input wr_en,
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output reg [31:0] rd_data,
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output [1:0] rd_guards /*verilator public*/,
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output [1:0] rd_guardsok /*verilator public*/,
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input clk
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);
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always @(posedge clk) begin
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if (wr_en)
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begin
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rd_data <= wr_data;
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end
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end
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// this initial statement will induce correct initialize behavior
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// initial rd_guards= { 2'b11 };
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assign rd_guards= {
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rd_data[0],
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1'b1
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};
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assign rd_guardsok[0] = 1'b1;
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assign rd_guardsok[1] = rd_data[0];
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endmodule // regfile
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