forked from github/verilator
49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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// bug1475
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module t (/*AUTOARG*/
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// Outputs
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ID_45, IDa_f4c,
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// Inputs
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clk, ID_d9f, IDa_657, ID_477
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);
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input clk;
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output reg ID_45;
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input ID_d9f;
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input IDa_657;
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output reg IDa_f4c;
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reg ID_13;
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input ID_477;
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reg ID_489;
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reg ID_8d1;
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reg IDa_183;
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reg IDa_91c;
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reg IDa_a96;
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reg IDa_d6b;
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reg IDa_eb9;
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wire ID_fc8 = ID_d9f & ID_13; //<<
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wire ID_254 = ID_d9f & ID_13;
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wire ID_f40 = ID_fc8 ? ID_8d1 : 0;
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wire ID_f4c = ID_fc8 ? 0 : ID_477;
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wire ID_442 = IDa_91c;
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wire ID_825 = ID_489;
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always @(posedge clk) begin
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ID_13 <= ID_f40;
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ID_8d1 <= IDa_eb9;
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ID_489 <= ID_442;
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ID_45 <= ID_825;
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IDa_d6b <= IDa_a96;
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IDa_f4c <= ID_f4c;
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if (ID_254) begin
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IDa_91c <= IDa_d6b;
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IDa_183 <= IDa_657;
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IDa_a96 <= IDa_657;
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IDa_eb9 <= IDa_183;
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end
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end
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endmodule
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