forked from github/verilator
89 lines
2.1 KiB
Systemverilog
89 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [7:0] a = crc[7:0];
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wire [7:0] b = crc[15:8];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] out; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[63:0]),
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// Inputs
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.clk (clk),
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.a (a[7:0]),
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.b (b[7:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h0908a1f2194d24ee
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, a, b
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);
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input clk;
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input [7:0] a;
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input [7:0] b;
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output reg [63:0] out;
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and u0[7:0] (out[7:0], a[7:0], b[7:0]);
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and u1[7:0] (out[15:8], a[0], b[7:0]);
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and u2[7:0] (out[23:16], a[0], b[0]);
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nand u3[7:0] (out[31:24], a[0], b[7:0]);
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or u4[7:0] (out[39:32], a[0], b[7:0]);
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nor u5[7:0] (out[47:40], a[0], b[7:0]);
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xor u6[7:0] (out[55:48], a[0], b[7:0]);
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xnor u7[7:0] (out[63:56], a[0], b[7:0]);
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endmodule
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