forked from github/verilator
17 lines
308 B
Systemverilog
17 lines
308 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t (/*AUTOARG*/);
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initial begin
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if (task_as_func(1'b0)) $stop;
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end
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task task_as_func;
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input ign;
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endtask
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endmodule
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