forked from github/verilator
53 lines
1019 B
Systemverilog
53 lines
1019 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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module t (clk);
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input clk;
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integer cyc; initial cyc=0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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ReadContDisps;
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end
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else if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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`ifndef verilator
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DispContDisps;
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`endif
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end
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task ReadContDisps;
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begin
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$display("%m: Here: %d", cyc);
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end
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endtask
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integer dindex;
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task DispContDisps;
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/* verilator public */
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begin
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if (cyc >= 2) begin
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if ( cyc >= 4 ) begin
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dindex = dindex + 2; //*** Error line
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$display("%m: DIndex increment %d", cyc);
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`ifdef VERILATOR
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$c("VL_PRINTF(\"Hello1?\\n\");");
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`endif
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end
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`ifdef VERILATOR
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$c("VL_PRINTF(\"Hello2?\\n\");");
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$c("VL_PRINTF(\"Hello3?\\n\");");
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`endif
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end
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end
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endtask
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endmodule
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