forked from github/verilator
75 lines
1.3 KiB
Systemverilog
75 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// verilator lint_off WIDTH
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// verilator lint_off VARHIDDEN
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module t (
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc; initial crc = 64'h1;
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chk chk (.clk (clk),
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.rst_l (1'b1),
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.expr (|crc)
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);
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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if (cyc==0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module chk (input clk, input rst_l, input expr);
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integer errors; initial errors = 0;
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task printerr;
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input [8*64:1] msg;
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begin
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errors = errors + 1;
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$write("%%Error: %0s\n", msg);
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$stop;
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end
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endtask
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always @(posedge clk) begin
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if (rst_l) begin
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if (expr == 1'b0) begin
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printerr("expr not asserted");
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end
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end
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end
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wire noxs = ((expr ^ expr) == 1'b0);
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reg hasx;
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always @ (noxs) begin
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if (noxs) begin
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hasx = 1'b0;
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end
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else begin
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hasx = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst_l) begin
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if (hasx) begin
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printerr("expr has unknowns");
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end
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end
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end
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endmodule
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