forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
18 lines
343 B
Systemverilog
18 lines
343 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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function recurse;
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input i;
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recurse = recurse2(i);
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endfunction
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function recurse2;
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input i;
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recurse2 = recurse(i);
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endfunction
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endmodule
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