verilator/test_regress/t/t_flag_context_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.

module t (/*AUTOARG*/);

   wire [2:0] foo = 5'b11111;

endmodule