forked from github/verilator
40 lines
1.1 KiB
Systemverilog
40 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off WIDTH
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typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;
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typedef enum integer {UP=0, UW=1'b1} UNSIZED;
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// verilator lint_on WIDTH
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localparam LEN = 3;
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localparam COL = 4;
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localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P)
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,LEN'(S), LEN'(E), LEN'(W), LEN'(P)
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,LEN'(S), LEN'(N), LEN'(W), LEN'(P)
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,LEN'(S), LEN'(N), LEN'(E), LEN'(P)
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,LEN'(S), LEN'(N), LEN'(E), LEN'(W)};
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bit [59:0] SE2 = {N, E, W, P
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,S, E, W, P
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,S, N, W, P
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,S, N, E, P
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,S, N, E, W};
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initial begin
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if (SEQ != 60'o32104210431043204321) $stop;
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if (SE2 != 60'o32104210431043204321) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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